1. Field of the Invention
The present invention generally relates to computer-aided circuit design systems, and more particularly to an electrical rules checker system and method for reporting problems with elements having tri-state logic conditions.
2. Discussion of the Related Art
Integrated circuits (ICs) are electrical circuits comprised of transistors., resistors, capacitors, and other components on a single semiconductor xe2x80x9cchipxe2x80x9d in which the components are interconnected to perform a variety of functions. Typical examples of ICs include, for example, microprocessors, programmable logic devices (PLDs), electrically erasable programmable memory devices (EEPROMs), random access memory devices (RAMs), operational amplifiers and voltage regulators. A circuit designer typically designs the IC by creating a circuit schematic indicating the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and to ensure that performance goals are satisfied.
In the world of electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer aided design (E-CAD) tools. As will be appreciated, electronic devices include electrical analog, digital, mixed hardware, optical, electro-mechanical, and a variety of other electrical devices. The design and subsequent simulation of any circuit board, very large scale integration chip, or other electrical device via E-CAD tools allows a product to be thoroughly tested and often eliminates the need for building a prototype. Thus, today""s sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without having to perform costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools utilize an electronic representation of the hardware device. A xe2x80x9cnetlistxe2x80x9d is one common representation of a hardware device. As will be appreciated by those skilled in the art of hardware device design, a xe2x80x9cnetlistxe2x80x9d is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
The two forms of a netlist are the flat netlist and the hierarchical netlist. Often, a netlist will contain a number of circuit xe2x80x9cmodulesxe2x80x9d which are used repetitively throughout the larger circuit. A flat netlist will contain multiple copies of the circuit modules essentially containing no boundary differentiation between the circuit modules and other components in the device. By way of analogy, one graphical representation of a flat netlist is simply the complete schematic of the circuit device.
In contrast, a hierarchical netlist will only maintain one copy of a circuit module, which may be used in multiple locations. By way of analogy, one graphical representation of a hierarchical netlist would show the basic and/or non-repetitive devices in schematic form and the more complex and/or repetitive circuit modules would be represented by xe2x80x9cblack boxes.xe2x80x9d As will be appreciated by those skilled in the art, a black box is a system or component whose inputs, outputs, and general function are known, but whose contents are not shown. These xe2x80x9cblack boxxe2x80x9d representations, hereinafter called xe2x80x9cmodules,xe2x80x9d will mask the complexities therein, typically showing only input/output ports.
An IC design can be represented at different levels of abstraction, such as at the Register-Transfer level (RTL) and the at logic level, using a hardware description language (HDL). VHDL and Verilog are examples of HDL languages. At any abstraction level, an IC design is specified using behavioral or structural descriptions, or a mix of both. At the logical level, the behavioral description is specified using Boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells are, among others, full-adders, logic gates, latches, and flip flops.
Set forth above is some very basic information regarding integrated circuits and other circuit schematics that are represented in netlists. Systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally such systems operate by identifying certain critical timing paths, then evaluating the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
One such system known in the prior art is marketed and commercially available under the name PathMill, by EPIC Design Technology, Inc., U.S.A. PathMill is a transistor-based analysis tool used to find critical paths and to verify timing in semiconductor designs. Using static and mixed-level timing analysis, the PathMill system processes transistors, gates, and timing models. It also calculates timing delays, performs path searches, and checks timing requirements. As is known, the PathMill system can analyze combinational designs containing gates, and sequential designs containing gates, latches, flip-flops, and clocks. Combinational designs are generally measured through the longest and shortest paths.
Illustrated in FIG. 1 is a block diagram of a prior art static timing analyzer system that illustrates the basic informational flow in such a system and that is generally denoted by reference numeral 2. Specifically, and as previously mentioned, one such system 2 is marketed under the name PathMill. FIG. 1 is a diagram that illustrates the informational flow in such a system 2. At the center of the diagram is a static timing analyzer 10, (i.e., the PathMill program). Surrounding this block 10 are a number of other blocks that represent various input and output files and/or information.
More particularly, the static timing analyzer 10 may utilize a configuration file 12, a file of timing models 14, one or more netlist files 16, a technology file 18, and a parasitic file 20, for various input information. In addition, the static timing analyzer 10 may generate a number of different output files or other output information, including a critical path report 22, a runtime log file 24, an error report 26, a software interface file 28, and a SPICE netlist 30. When started, the static timing analyzer 10 first processes the input netlist file(s) 16, the technology file 18, and the configuration files 12. The information from these files is subsequently used for performing path analyses. Since the static timing analyzer 10, (i.e., the PathMill program) is publicly available and marketed, its function and operation are well known, and therefore need not be discussed in detail herein.
While tools such as these are useful for the design verification process after layout, there are various shortcomings in the static timing analyzer 10, (i.e. the PathMill program) and other similar products. These shortcomings include, but are not limited to, the ability to identify the probable identity of unknown logic gates or particular combinations of logic gates of the circuit. This is because of the pervasive problems in rules checking programs that are unable to inclusively determine all of the time whether certain parts of a design are actually certain types of structures.
With this uncertainty the rules checker program cannot completely certify the circuit design. More specifically, there is sometimes a need to identify combinations of gates that are configured in such a manner that may lead to operational uncertainty or performance problems. There are various reasons why such a gate identification may be desirable, which will be appreciated by those skilled in the art.
There is a need to establish the quality assurance of those elements that are assigned a probable identity. This allows a user to validate the quality of the assumed identity of the circuit identified as a probable structure type. There is some need in the design verification process to communicate errors with regard to identified and probable elements that are positively identified and elements that are identified as probable circuit configurations.
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.
The present invention provides an electrical rules checker system and method for reporting any error discovered during appraisal of an element at a node in a netlist. Tri-state logic is one or more logic elements that can be identified positively as being in a particular circuit configuration, identified probably as being in a particular circuit configuration and not identified positively as being in a particular circuit configuration.
Briefly described, in architecture, the electrical rules checker can be implemented as follows. A first code segment selects a circuit configuration to be identified. A second code segment identifies any element at a node, equal to said circuit configuration, and a third code segment identifies any element at the node virtually equal to said circuit configuration. A fourth code segment appraises the element equal to and virtually equal to the circuit configuration, and a fifth code segment reports any error discovered during appraisal of the element at the node.
The present invention can also be viewed as providing a method for reporting any error discovered during appraisal of an element at a node in a netlist. In this regard, the method can be broadly summarized by the following steps: (1) selecting a circuit configuration to be identified; (2) identifying any element at a node, equal to said circuit configuration; (3) identifying any element at the node virtually equal to said circuit configuration; (4) appraising said clement equal to and virtually equal to said circuit configuration; and (5) reporting any error discovered during appraising of said element at the node.